A high level modeling system (HLMS) is a software tool in which electronic designs can be described, simulated, and translated by machine into a design realization. An HLMS provides a higher level of abstraction for describing an electronic circuit than a hardware description language (HDL) simulation environment such as the ModelSim environment from the Model Technology company. An HLMS generally provides a mathematical representation of signals as compared to standard logic vectors in a hardware description language (HDL). It is desirable for the high-level abstractions to be precisely correlated with the ultimate implementation representation, both in simulation semantics and in implementation. The Xilinx System Generator tool for DSP and the MathWorks' Simulink and MATLAB environments are example HLMS's in which such capabilities are desirable.
An HLMS for electronic circuit design generally offers abstractions that are not available in traditional HDLs. For example, an HLMS is likely to offer abstractions that relate to signal propagation and signal state, while an HDL may support a detailed representation that more closely models a realized electronic circuit. An electronic design modeled in an HLMS may be viewed as a collection of components that communicate through signals. Signals are discrete, time-varying sequences of values. An HLMS generally provides abstractions to support implementing synchronous designs without requiring the specification of explicit references to clocks or clock signals. Instead of providing a detailed, event driven simulation, an HLMS may also provide abstractions wherein clock-synchronous state changes are scheduled to occur at regular intervals and in which there is no notion of the timing characteristics related to the intended implementation as an electronic circuit. In further support of creating high-level designs, an HLMS may also represent state in terms of numerical (or other abstract) values instead of representing state in a detailed format analogous to standard logic vectors.
An HDL generally supports the detailed specification of timing characteristics and multi-valued signal states for a circuit. Example timing characteristics include propagation delays, setup times, and hold times, and example signal states include the standard binary logic types as well as strongly and weakly-driven states, a transitional state, an unknown state, and an uninitialized state. HDL simulators generally are capable of modeling such systems, which affects both the way events are handled (times at which signal states change) and the way the system state is presented at any given time. HDL simulations are typically event driven and require system inputs or outputs to be specified in terms of a standard extended type (e.g., the standard logic vectors of VHDL/IEEE 1164).
In an HLMS-based design, there may be some components that are described in an HDL. It is often desirable to simulate the HDL components while simulating the HLMS-based design. The process of incorporating an HDL simulation into an HLMS-based simulation is referred to as co-simulation. To effectively simulate both the high-level components and the HDL components, it would desirable to minimize the impact of disparities between the data types supported by the HLMS and the possible signal states supported by the HDL simulator and provide realistic timing relationships between the HLMS and the HDL simulator.
A method and an apparatus that address the aforementioned problems, as well as other related problems, are therefore desirable.